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Certification Course · Executive Certification in ASIC Verification

Executive Certification in ASIC Verification

9 Months

Fee
₹2,00,000 + GST
Schedule
9 Months
Seats
100
Enrolled
22
Trainer
MAVEN silicon
Rating
★ 4.5
Apply now 100 seats
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Overview

About this course

About the Course:

In today’s AI era, chip designers have access to AI-powered EDA tools, silicon-proven IP libraries, and open computing platforms like RISC-V Open ISA, enabling them to design powerful, innovative SoCs efficiently. With these advancements, even the most complex SoCs can be realized for next-generation electronic products. However, thorough verification is critical to ensure the success of newly designed chips and systems. This makes it the perfect time for chip designers and VLSI enthusiasts to delve into ASIC verification methodologies and learn how to verify IPs, subsystems, and complete SoCs effectively. The course covers the complete spectrum of VLSI verification skills, starting with ASIC verification methodologies. It progresses to Advanced Verilog, Code Coverage, SystemVerilog, SystemVerilog Assertions (SVA), followed by Formal Verification, including FPV, formal algorithms, equivalence checking, with detailed case studies. The course then explores UVM - covering TB architecture, factory, phases, TLM Ports, sequences, virtual sequences and RAL, Gate-Level Simulation (GLS), Timing Verification, SDF annotation, Debugging, regression, low-power verification with UPF, Portable Stimulus Standard (PSS) for test scenario modelling, SoC verification methodology with various case studies. In addition, it also covers Python for DV automation, C programming for writing firmware SoC testcases, and Generative AI for RTL design and verification - empowering engineers with AI-assisted design and verification capabilities. This hands-on course ensures that the participants build strong foundations in Design Verification – functional verification, low-power and formal verification, GLS, DV automation, and SoC verification, while gaining hands-on expertise through labs, case studies, and real-world verification projects.



Outcomes

What you'll achieve

  • Anyone with a bachelor’s degree and a passion for VLSI
  • Professionals looking to grow their career in VLSI
  • Any IT Professional with a bachelor’s degree looking to transition into VLSI design and semiconductor technologies
  • Project/Product Managers aiming to transition into or deepen their understanding of VLSI and chip design
  • Engineers who aspire to use industry-standard EDA tools and build their own chips from concept to layout
  • Hands-On Training
  • Self Paced & Live Sessions
  • 24/7 Lab & EDA Tool Access
  • Certification from iHUB, IIT Roorkee
  • 750+ Hrs of Live Online Immersive Learning Journey
  • Exploring Cutting-edge Applications of Artificial Intelligence in VLSI – A Key Focus Area
  • 70% Hands On , 30% Theory
  • Master Classes from IIT Faculty and Industry Experts
  • 2 Days Campus Immersion
  • Business Communication (Aptitude & Soft Skill Training)
  • Career Support Services
  • 24/7 EDA Tools Access (Cadence, Synopsis, Siemens )
  • 24/7 Access to e-Learn cloud-based platform
  • Student Success Support

Curriculum

Download the course curriculum

Voices

Learner testimonials

  •  Timescale System Task
  • Generate Blocks
  • Self-checking Testbench
  • Named Events
  • Verilog Stratified Event Queue
  • Statement Coverage
  • Branch Coverage
  • Toggle Coverage
  • Finite State Machine Coverage
  • Hands-On Labs
Module 1

Module 1

Advanced Verilog and Code Coverage

  • Verification Essentials
  • DV concepts and flow
  • Testplan
  • Directed Vs Random Testcases
  • Constraint Random Coverage Driven Verification [ CRCDV ] 
Module 2

Module 2

ASIC Verification Methodology

  • RISC-V processor overview
  • RISC-V ISA overview
  • RV32I – R Type Instruction
  • RV32I – I Type Instruction
  • RV32I – S & B Type Instructions
  • RV-32I – J & U Type Instructions
  • RV32I – Assembly programs and Summary
Module 3

Module 3

RISC-V Instruction Set Architecture

  • Different types of Operating System
  • Design Features & layers
  • Basic Linux commands
  • Advanced commands
  • Utilities
  • Vi editor
  • Networking in Linux
  • Hands-On Labs
Module 4

Module 4

Linux Operating System

  • Types of Version Control System
  • Git - Basic Workflow
  • Git - Various commands
  • Git - Branching & Merging
  • Git - Configuration
  • Hands-On Labs 
Module 5

Module 5

GIT Version Control System [ VCS ]

  •  SystemVerilog Datatypes
  • SystemVerilog Memories
  • SystemVerilog Tasks & Functions
  • Object Oriented Programming - Basic
  • Object Oriented Programming - Advanced
  • SV Randomization
  • SV Threads, Mailbox and Semaphores
  • SV Virtual Interfaces
  • Functional Coverage
  • Case Studie
  • s Hands-On Labs
Module 6

Module 6

SystemVerilog HVL

  • Different types of assertions
  • Sequences
  • Different Operators & Sequence Compositions
  • Definition of reusable sequences and properties
  • Connecting Assertions to DUT
  • SVA Coverage and Control Tasks
  • Hands-On Lab
Module 7

Module 7

SystemVerilog Assertions

  • Emergence of Formal Verification
  • Formal Verification Algorithms
  • Formal Property Verification
  • Formal Equivalance Checking
  • Types of Equivalence Checking
  • Hands-On Labs
Module 8

Module 8

Formal Verification

  • UVM Overview
  • UVM TB Architecture and Base Class Hierarchy
  • UVM Factory
  • Stimulus Modelling & Testbench Overview
  • UVM Phases and Reporting Mechanism
  • TLM Ports and Configuration
  • Creation of UVM TB Components
  • UVM Sequences
  • Virtual Sequences & Virtual Sequencers
  • UVM Events & Callbacks
  • Creating Scoreboard in UVM
  • Hands-On Labs
Module 9

Module 9

Universal Verification Methodology [ UVM ]

  • GLS Timing Verification
  • GLS TB Setup and Environment
  • SDF Annotation
  • GLS Overhead
  • Improving GLS Performance
  • GLS Simulation Debugging
  • GLS Regression and Verification Signoff
  • Case Study 
Module 10

Module 10

Gate Level Simulation [ GLS

  • Necessity of Low Power
  • Unified Power Format [ UPF ]
  • Modeling Power Intent in UPF
  • Static Low Power Verification with UPF
  • Dynamic Low Power verification with UPF
  • Advanced UPF-Based Verification
  • Hands-On Labs 
Module 11

Module 11

Low Power Verification

  • PSS Basics
  • PSS Constructs
  • Test Scenario Modeling
  • Coverage in PSS
  • Integration with Verification Methodologies
  • Advanced PSS Concepts
  • Case Study 
Module 12

Module 12

Portable Stimulus Standard [ PSS ]

  • C Programming
  • SoC Verification Methodology
  • Case Study
Module 13

Module 13

SoC Verification

  • Introduction to Gen AI
  • Large Language Models
  • Prompt Engineering
  • Model Fine Tuning and Domain-based models for VLSI
  • Gen AI for VLSI
  • ML for EDA 
Module 14

Module 14

Gen AI for VLSI

  • Python Programming Basics
  • Python Fundamentals for DV
  • Python for Regression Testing
  • Log Parsing and Report Generation
  • Case Study
Module 15

Module 15

Python for DV Automation

  • Transition from College to Corporate
  • Interpersonal Skills and Presentation Skills
  • Email Etiquette
  • Resume Writing
  • Mock Interviews: Technical/HR
  • Interview Skills: Group Discussion and HR Round Preparation
Module 16

Module 16

Business communication

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