Certification Course · Executive Certification in VLSI Design for Testing

Executive Certification in VLSI Design for Testing

9 Months

Fee: ₹2,00,000 + GST
Schedule: 9 Months
Seats: 100
Enrolled: 42
Trainer: MAVEN silicon
Rating: ★ 4.5

Apply now 100 seats

Overview

About this course

About the Course:

In the AI era, chip designers are empowered with AI-powered EDA tools, silicon-proven IP libraries, and open computing platforms like RISC-V, enabling the efficient design of powerful SoCs for next-generation products. However, ensuring testability and fault coverage is equally critical for first-pass silicon success. This is the right time for chip designers and VLSI enthusiasts to explore ASIC Design for Testing (DFT) methodologies—covering scan insertion, ATPG, fault modeling, BIST, boundary scan, JTAG, and advanced techniques for low-power and high-performance designs. A strong foundation in DFT ensures high-quality, reliable SoCs ready for mass production.
This course provides a comprehensive foundation in Design For Testing. Learners begin with an overview of VLSI, Moore’s Law, SoC architecture, and design flows, followed by digital logic fundamentals such as number systems, combinational and sequential circuits, FSMs, and memory design. The course advances into practical hardware design and verification using Verilog HDL programming - coding styles, FSM design, and lab exercises. It then walks you through CMOS fundamentals, Synthesis, Clock Domain Crossing, STA, Equivalence Checking, and Physical Design Flow - floor planning, placement, CTS, routing, layout compaction, and physical verification (DRC, LVS, IR drop, EM), with labs and case studies.
The Design For Testing module covers verification vs testing, scan insertion, ATPG, fault modelling, BIST, boundary Scan, Test compression, DRC & Test coverage, JTAG, DFT for Analog Macros, while automation skills are developed with Tcl and Python scripting. Students also learn version control with Git, before progressing to advanced DFT concepts and doing an industry standard project – DFT implementation on an SoC.

Outcomes

What you'll achieve

Anyone with a bachelor’s degree and a passion for VLSI
Professionals looking to grow their career in VLSI
Any IT Professional with a bachelor’s degree looking to transition into VLSI design and semiconductor technologies
Project/Product Managers aiming to transition into or deepen their understanding of VLSI and chip design
Engineers who aspire to use industry-standard EDA tools and build their own chips from concept to layout

Online - Self Paced and Live Sessions
2 Days Campus Immersion Program*
iHUB DivyaSampark, IIT Roorkee Certification.
24/7 Lab & EDA Tool Access
Master Classes from IIT Faculties or Industry Experts
Career Support Services*
750+ Hrs of Live Online Immersive Learning Journey
Exploring Cutting-edge Applications of Artificial Intelligence in VLSI – A Key Focus Area
70% Hands On , 30% Theory
Master Classes from IIT Faculty and Industry Experts
Business Communication (Aptitude & Soft Skill Training)
iHub Divya Sampark- IIT Roorkee Certification
Business Communication (Aptitude & Soft Skill Training)
Career Support Services
24/7 EDA Tools Access (Cadence, Synopsis, Siemens )
24/7 Access to e-Learn cloud-based platform
Student Success Support

Curriculum

Download the course curriculum

Voices

Learner testimonials

VLSI Technology Overview
Moore’s Law
IP, Subsystems, and Chips
SoC Architecture
SoC Design Process
System-Level Design - Hardware
& Software
Semiconductor Industry Overview
Module 1
VLSI SoC Design

Different types of Operating System
Design Features & layers
Basic Linux commands
Advanced commands
Utilities
Vi editor
Networking in Linux
Hands-On Labs
Module 5
Linux Operating System

Number Systems
Logic Gates
Designing Combinational Logic Circuits
Latches, Flipflops and Flipflop
Conversions
Registers & Counters
Frequency Dividers
Finite State Machines
Mealy & Moore FSMs
Sequential circuits using Finite
State Machines
Memories and Programmable
Logic Devices.
Asynchronous Sequential Circuits
Module 3
Advanced Digital Design

RISC-V processor overview
RISC-V ISA overview
RV32I – R Type Instruction
RV32I – I Type Instruction
RV32I – S & B Type Instructions
RV-32I – J & U Type Instructions
RV32I – Assembly programs
Module 4
RISC-V Instruction Set Architecture

VLSI Design Flow
ASIC Vs FPGA
Module 2
SoC ASIC Design Flow

Introduction to EDA tools
Data Types
Verilog Operators
Advanced Verilog for Verification
Assignments
Synthesis Coding Styles
Finite State Machine
Hands-On Labs
Module 6
Verilog HDL

MOSFET
CMOS Fabrication
CMOS Characteristics
CMOS Circuit Design
CMOS Transistor Sizing
Stick Diagrams and Layouts
Non-Ideal Characteristics
Hands-On Labs
Module 7
CMOS Fundamentals

Introduction to Clock Domain
Crossing [ CDC ]
Different types of Synchronizers
CDC Analysis
Types of CDC errors
CDC Verification flow
Case Study
Module 8
Clock Domain Crossing

Introduction to Reset Domain
Crossing [ RDC ]
RDC Hazards and Issues
RDC Verification Techniques
Case Study
Module 9
Reset Domain Crossing

Types of Timing Analysis
STA in Design Flow
Different Timing Parameters
Techniques to improve Timing
Timing Analysis Procedures
Setup & Hold time violations
Eliminate Setup & Hold time violations
Hands-On Labs
Module 10
Static Timing Analysis [ STA ]

Datatypes
Operators
Conditional branches
Controlled loops
Subroutines
Special Variables
File Operations
Regular expressions
Processes
Modules & Packages
Assignments
Hands-On Labs
Module 11
Perl Scripting

Datatypes and Operators
Functions and Loops
Python OOP
Exceptions
File IO Operations
Sequences and Methods
Hands-On Labs
Module 12
Python

Types of Version Control System
Git - Basic Workflow
Git - Various commands
Git - Branching & Merging
Git - Configuration
Hands-On Labs
Module 13
GIT Version Control System [ VCS ]

Design Styles
Partitioning
Floorplanning
Placement
Clock Tree Synthesis [ CTS ]
Routing
Static Timing Analysis [ STA ]
Module 14
Physical Design - Overview

Importance of Testing
Outcome of Testing
ASIC Design Flow & Testing
Verification Vs Testing
Defect Vs Fault
Module 15
Design for Testing [ DFT ]

Types of Testing
Testing at different Abstraction Levels
Fault Modelling and Collapsing
ATPG Basics
Combinational ATPG
Tessent Shell Introduction
Fault Class
ATPG Basics
Hands-On Labs
Module 16
Automatic Test Pattern Generator ( ATPG )

Tessent Shell Usage
Additional Fault Models
Hands-On Labs
Module 17
Fault Models

Introduction to DFT
Scan Chain Insertion
Hands-On Lab
Module 18
Scan Chain Insertion

Test Compression Techniques
Hands-On L
Module 19
Test Compression

Boundary Scan Architecture
Boundary Scan Instructions
Boundary Scan Applications
Hands-On Labs
Module 20
Boundary Scan

Introduction to BIST
Logic BIST [ LBIST ]
Memory BIST [ MBIST ]
Hands-On Lab
Module 21
Built In Self Test [ BIST ]

IJTAG Architecture
Hand
Module 22
IJTAG

Sources of Power Consumption
Different Techniques for Lowering
Power Consumption
Transistor resizing
Clock Gating
Sleep Transistors
Transistor reordering
Dynamic Voltage/Frequency Scaling
Isolation Cells and Level Shifters
Precomputation
Power Oriented Programming
Low Power Design Methodology (UPF)
Hands-On Labs
Module 23
Low Power Design

Design Rule Checks
Improving Test Coverage
Fault Diagnosis
Hands-On Labs
Module 24
DRC & Test Coverage

DFT for Analog Macros
Hands-On Labs
Module 25
DFT for Analog Macros

Introduction to Gen AI
Large Language Models
Prompt Engineering
Model Fine Tuning and Domain-based
models for VLSI
Gen AI for VLSI
ML for EDA
Module 26
Gen AI for VLSI

Transition from College to Corporate
Interpersonal Skills and
Presentation Skills
Email Etiquette
Resume Writing
Mock Interviews: Technical/HR
Interview Skills: Group Discussion
and HR Round Preparation
Module 27
Business communication