Executive Certification in RISC-V IP Design

• RISC-V Overview
• RISC-V ISA - Base ISA, RV32I Instructions, Extensions
• RISC-V Privilege Levels
• Machine ISA
• Supervisor ISA
• Hypervisor ISA
• PMA, PMP

• Introduction to RISC-V Debug
• RISC-V Debug System
• RISC-V Debug Control and Status Registers [ CSR's ]
• Debug Process

• Introduction to Platform Level Interrupt Controller [ PLIC ]
• PLIC Operations and Various Registers

• Application Binary Interface [ ABI ]
• Supervisor Binary Interface [ SBI ]
• RISC-V Assembly Programming
• RISC-V Toolchain
• Demo on RISC-V toolchain flow

• Memory Hierarchy
• Locality of reference
• Cache Associativity
• Cache Policies
• Cache Coherency Protocols

• Introduction to Virtual Memory
• Address Translation and Page Table Walk
• Translation Lookaside Buffer [ TLB ]

• Basics of CPU and role in a computing system
• RISC vs. CISC architectures
• Instruction Set Architecture (ISA) overview
• Components of a CPU
• Memory Hierarchy Interaction
• Instruction Execution Cycle
• Pipelined Design
• Hazards in Pipelining
• Advanced Pipelining Techniques
• Performance Analysis

• RISC-V RV32I RTL Architecture Design
• RISC-V RV32I 5 Stage Pipelined RTL Design

• Introduction to EDA tools
• Data Types
• Verilog Operators
• Advanced Verilog for Verification
• Assignments
• Synthesis Coding Styles
• Finite State Machine
• Hands-On Labs

• Timescale System Task
• Generate Blocks
• Self-checking Testbench
• Named Events
• Verilog Stratified Event Queue
• Statement Coverage
• Branch Coverage
• Toggle Coverage
• Finite State Machine Coverage
• Hands-On Labs

• Introduction to RTL Linting
• Coding Guidelines and Standards
• Common RTL Lint Checks
• Hands-On Labs

• Introduction to Logic Synthesis
• Constraints and Timing
• Optimization Techniques
• Hands-On Labs

• Logic Equivalance Checking Flow
• Constraints Handling
• Equivalance Checking Methodology
• Hands-On Labs

• Introduction to Clock Domain Crossing [ CDC ]
• Different types of Synchronizers
• CDC Analysis
• Types of CDC errors
• CDC Verification flow
• Case Study

• Introduction to Reset Domain Crossing [ RDC ]
• RDC Hazards and Issues
• RDC Verification Techniques
• Case Study

• Sources of Power Consumption
• Different Techniques for Lowering Power Consumption
• Transistor resizing
• Clock Gating
• Sleep Transistors
• Transistor reordering
• Dynamic Voltage/Frequency Scaling
• Isolation Cells and Level Shifters
• Precomputation
• Power Oriented Programming
• Low Power Design Methodology (UPF)
• Hands-On Labs

• Data Types
• Operators
• Procedural Blocks
• Procedural Statements
• Tasks and Functions
• Packages
• Arrays
• Interfaces
• Hands-On Labs

• Verification Essentials
• DV concepts and flow
• Testplan
• Directed Vs Random Testcases
• Constraint Random Coverage Driven Verification [ CRCDV ]

• Different types of Assertions
• Sequences
• Different Operators & Sequence Compositions
• Definition of reusable Sequences and Properties
• Connecting Assertions to DUT
• SVA Coverage and Control Tasks
• Hands-On Labs

• Emergence of Formal Verification
• Formal Verification Algorithms
• Formal Property Verification
• Formal Equivalance Checking
• Types of Equivalence Checking
• Hands-On Labs

• Introduction to Gen AI
• Large Language Models
• Prompt Engineering
• Model Fine Tuning and Domain-based models for VLSI
• Gen AI for VLSI
• ML for EDA

• Transition from College to Corporate
• Interpersonal Skills and Presentation Skills
• Email Etiquette
• Resume Writing
• Mock Interviews: Technical/HR
• Interview Skills: Group Discussion
• and HR Round Preparation