Certification Course · Executive Certification in RISC-V IP Verification
Executive Certification in RISC-V IP Verification
9 Months
- Fee
- ₹1,50,000 + GST
- Schedule
- 9 Months
- Seats
- 100
- Enrolled
- 33
- Trainer
- MAVEN silicon
- Rating
- ★ 4.5
Overview
About this course
The RISC-V Processor is becoming very popular and influential, like the open-source operating system Linux, as it's based on the RISC-V open ISA [Instruction Set Architecture] - open and license-free. In this AI era, chip designers are empowered with open computing solutions like RISC-V Open ISA to design powerful AI chips using various processors and accelerators. As RISC-V Open ISA democratizes processor design, chip designers can now dream of independently creating their own processors and chips with their innovations. So, it's the right time for chip designers and VLSI enthusiasts to explore the RISC-V Open ISA and how to design a RISC-V processor.
This course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture - Machine, Supervisor and Hypervisor ISAs, RISC-V Standard Extensions, Interrupts, PMP, and RISC-V Debug. Also, as part of this hands-on course, you will learn CPU architecture, RISC-V IP Verification using SystemVerilog and UVM, ASIC Verification Methodologies, Formal Verification, Low Power Verification, Portable Stimulus Standard, with various Case Studies.
In this course you will verify a multi-stage RISC-V Pipeline Processor – exploring RTL IP verification using formal verification, SystemVerilog, UVM, and RISC-V CPU compliance testing. This project experience will help you deal with verifying any complex RISC-V CPUs and IPs, and creating Verification IPs.
Outcomes
What you'll achieve
- Anyone with a bachelor’s degree and a passion for VLSI
- Professionals looking to grow their career in VLSI
- Any IT Professional with a bachelor’s degree looking to transition into VLSI design and semiconductor technologies
- Project/Product Managers aiming to transition into or deepen their understanding of VLSI and chip design
- Engineers who aspire to use industry-standard EDA tools and build their own chips from concept to layout
- Online - Self Paced and Live Sessions
- 24/7 Lab & EDA Tool Access
- 2 Days Campus Immersion Program*
- Master Classes from IIT Faculties or Industry Experts
- iHUB DivyaSampark, IIT Roorkee Certification.
- Career Support Services*
- 750+ Hrs of Live Online Immersive Learning Journey
- Exploring Cutting-edge Applications of Artificial Intelligence in VLSI – A Key Focus Area
- 70% Hands On , 30% Theory
- Business Communication (Aptitude & Soft Skill Training)
- 24/7 EDA Tools Access (Cadence, Synopsis, Siemens )
- 24/7 Access to e-Learn cloud-based platform
- Student Success Support
Curriculum
Download the course curriculum
Voices
Learner testimonials
- RISC-V Overview
- RISC-V ISA - Base ISA, RV32I Instructions, Extensions
- RISC-V Privilege Levels
- Machine ISA
- Supervisor ISA
- Hypervisor ISA
- PMA, PMP
- Introduction to RISC-V Debug
- RISC-V Debug System
- RISC-V Debug Control and Status Registers [ CSR's ]
- Debug Process
- Introduction to Platform Level Interrupt Controller [ PLIC ]
- PLIC Operations and Various Registers
- Application Binary Interface [ ABI ]
- Supervisor Binary Interface [ SBI ]
- RISC-V Assembly Programming
- RISC-V Toolchain
- Demo on RISC-V toolchain flow
- Memory Hierarchy
- Locality of reference
- Cache Associativity
- Cache Policies
- Cache Coherency Protocols
- Introduction to Virtual Memory
- Address Translation and Page Table Walk
- Translation Lookaside Buffer [ TLB ]
- Basics of CPU and role in a computing system
- RISC vs. CISC architectures
- Instruction Set Architecture (ISA) overview
- Components of a CPU
- Memory hierarchy interaction
- Instruction Execution Cycle
- Pipelined Design
- Hazards in Pipelining
- Advanced Pipelining Techniques
- Performance Analysis
- RISC-V RV32I RTL Architecture Design
- RISC-V RV32I 5 Stage Pipelined RTL Design
- Timescale System Task
- Generate Blocks
- Self-checking Testbench
- Named Events
- Verilog Stratified Event Queue
- Statement Coverage
- Branch Coverage
- Toggle Coverage
- Finite State Machine Coverage
- Hands-On Labs
- Verification Essentials
- DV concepts and flow
- Testplan
- Directed Vs Random Testcases
- Constraint Random Coverage Driven Verification [ CRCDV ]
- SystemVerilog Datatypes
- SystemVerilog Memories
- SystemVerilog Tasks & Functions
- Object Oriented Programming - Basic
- Object Oriented Programming - Advanced
- SV Randomization
- SV Threads, Mailbox and Semaphores
- SV Virtual Interfaces
- Functional Coverage
- Case Studies
- Hands-On Labs
- Different types of Assertions
- Sequences
- Different Operators & Sequence Compositions
- Definition of reusable Sequences and Properties
- Connecting Assertions to DUT
- SVA Coverage and Control Tasks
- Hands-On Labs
- Emergence of Formal Verification
- Formal Verification Algorithms
- Formal Property Verification
- Formal Equivalance Checking
- Types of Equivalence Checking
- Hands-On Labs
- UVM Overview
- UVM TB Architecture and Base Class Hierarchy
- UVM Factory
- Stimulus Modelling & Testbench Overview
- UVM Phases and Reporting Mechanism
- TLM Ports and Configuration
- Creation of UVM TB Components
- UVM Sequences
- Virtual Sequences & Virtual Sequencers
- UVM Events & Callbacks
- Creating Scoreboard in UVM
- Hands-On Labs
- Necessity of Low Power
- Unified Power Format [ UPF ]
- Modeling Power Intent in UPF
- Static Low Power Verification with UPF
- Dynamic Low Power verification with UPF
- Advanced UPF-Based Verification
- Hands-On Labs
- PSS Basics
- PSS Constructs
- Test Scenario Modeling
- Coverage in PSS
- Integration with Verification Methodologies
- Advanced PSS Concepts
- Case Study
- Compliance Test framework
- Running Compliance Tests
- Introduction to Gen AI
- Large Language Models
- Prompt Engineering
- Model Fine Tuning and Domain-based models for VLSI
- Gen AI for VLSI
- ML for EDA
- Transition from College to Corporate
- Interpersonal Skills and Presentation Skills
- Email Etiquette
- Resume Writing
- Mock Interviews: Technical/HR
- Interview Skills: Group Discussion
- and HR Round Preparation