Certification Course · Executive Post Graduate Certification in VLSI SoC Design and Verification
Executive Post Graduate Certification in VLSI SoC Design and Verification
12 Months
- Fee
- ₹2,00,000 + GST
- Schedule
- 12 Months
- Seats
- 100
- Enrolled
- 56
- Trainer
- MAVEN silicon
- Rating
- ★ 4.5
Overview
About this course
The RISC-V Processor is becoming very popular and influential, like the open-source operating system Linux, as it's based on the RISC-V open ISA [Instruction Set Architecture] - open and license-free. In this AI era, chip designers are empowered with open computing solutions like RISC-V Open ISA to design powerful AI chips using various processors and accelerators. As RISC-V Open ISA democratizes processor design, chip designers can now dream of independently creating their own processors and SoCs with their innovations. So, it's the right time for chip designers and VLSI enthusiasts to explore the RISC-V Open ISA and how to design a RISC-V SoC.
This course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture - Machine, Supervisor and Hypervisor ISAs, RISC-V Standard Extensions, Interrupts, PMP, and RISC-V Debug. Also, as part of this hands-on course, you will learn ARM ISA, SoC architecture, SoC Design Methodology, RISC-V SoC RTL Design using Verilog and SystemVerilog, RISC-V SoC RTL Verification using UVM, SoC interface protocols - AMBA [AXI, AHB, APB], SPI, UART, I2C, GPIO, Portable stimulus standard, Low power design and verification, with various Case Studies.
In this course you will design and verify a RISC-V SoC – exploring SoC RTL design using Verilog and SystemVerilog, SoC RTL verification using UVM. Also, you will implement the SoC - exploring ASIC design flow - Synthesis, DFT, and PD. This project experience will help you deal with designing any complex SoCs.
Outcomes
What you'll achieve
- Anyone with a bachelor’s degree and a passion for VLSI
- Professionals looking to grow their career in VLSI
- Any IT Professional with a bachelor’s degree looking to transition into VLSI design and semiconductor technologies
- Project/Product Managers aiming to transition into or deepen their understanding of VLSI and chip design
- Engineers who aspire to use industry-standard EDA tools and build their own chips from concept to layout
- Online - Self Paced and Live Sessions
- 24/7 Lab & EDA Tool Access
- 2 Days Campus Immersion Program*
- Master Classes from IIT Faculties or Industry Experts
- iHUB DivyaSampark, IIT Roorkee Certification.
- Career Support Services*
- 750+ Hrs of Live Online Immersive Learning Journey
- Exploring Cutting-edge Applications of Artificial Intelligence in VLSI – A Key Focus Area
- 70% Hands On , 30% Theory
- Business Communication (Aptitude & Soft Skill Training)
- 24/7 Access to e-Learn cloud-based platform
- Student Success Support
Curriculum
Download the course curriculum
Voices
Learner testimonials
- VLSI Technology Overview
- Moore’s Law
- IP, Subsystems, and Chips
- SoC Architecture
- SoC Design Process
- System-Level Design - Hardware & Software
- Semiconductor Industry Overview
- VLSI Design Flow
- ASIC Vs FPGA
- Microcontrollers Vs Complex SoCs
- Computer System Architecture - Von Neuman Vs Harvard
- SoC Design Considerations
- RISC-V ISA Overview
- RISC-V Toolchain
- Memories - Physical Vs Virtual
- MMUs and Interrupt Controllers
- Introduction to Memories
- Volatile Memories
- Non-Volatile Memories
- Memory Controllers
- Memory Hierarchy
- Locality of reference
- Cache Associativity
- Cache Policies
- Cache Coherency Protocols
Features of OS
- Introduction to Virtual Memory
- Address Translation and Page Table Walk
- Translation Lookaside Buffer [ TLB ]
- RISC-V Overview
- RISC-V ISA - Base ISA, RV32I Instrcutions, Extensions
- RISC-V Privilege Levels
- Machine ISA
- Supervisor ISA
- Hypervisor ISA
- PMA, PMP
- Introduction to RISC-V Debug
- RISC-V Debug System
- RISC-V Debug Control and Status Registers [ CSR's ]
- Debug Process
- Introduction to Platform Level Interrupt Controller [ PLIC ]
- PLIC Operations and Various Registers
- Application Binary Interface [ ABI ]
- Supervisor Binary Interface [ SBI ]
- RISC-V Assembly Programming
- RISC-V Toolchain
- Demo on RISC-V toolchain flow
- RISC-V RV32I RTL Architecture Design
- RISC-V RV32I 5 Stage Pipelined RTL Design
- Introduction to EDA tools
- Data Types
- Verilog Operators
- Advanced Verilog for Verification
- Assignments
- Synthesis Coding Styles
- Finite State Machine
- Hands-On Labs
- SystemVerilog Datatypes
- SystemVerilog Memories
- SystemVerilog Tasks & Functions
- Object Oriented Programming - Basic
- Object Oriented Programming - Advanced
- SV Randomization
- SV Threads, Mailbox and Semaphores
- SV Virtual Interfaces
- Functional Coverage
- Case Studies
- Hands-On Labs
- UVM Overview
- UVM TB Architecture and Base Class Hierarchy
- UVM Factory
- Stimulus Modelling & Testbench Overview
- UVM Phases and Reporting Mechanism
- TLM Ports and Configuration
- Creation of UVM TB Components
- UVM Sequences
- Virtual Sequences & Virtual Sequencers
- UVM Events & Callbacks
- Creating Scoreboard in UVM
- Hands-On Labs
- ARM Registers
- ARM Instruction Set Architecture
- ARM Exceptions and Handling
- ARM Secure and Non-Secure Models
- ISA Extensions
- ARM Memory Model
- ARM Debug Interfaces
- Debug features
- Trace and Monitoring
- Secure and Non-Secure Debug
- Introduction to Procedure Call Standards
- ARM software interfaces with Operating Systems
- Advanced eXtensible Bus [ AXI ]
- Advanced High-Performance bus [ AHB ]
- Advnaced Peripheral Bus [ APB ]
- Coherency Hub Int
- Universal Asynchronous Receiver Transmitter [ UART ]
- Serial Peripheral Interface [ SPI ]
- Inter-Integrated Circuit [ I2C ]
- General Purpose Input Output [ GPIO ]
- Joint Test Action Group [ JT
- Sources of Power Consumption
- Different Techniques for Lowering Power Consumption
- Transistor resizing
- Clock Gating
- Necessity of Low Power
- Unified Power Format [ UPF ]
- Modeling Power Intent
- Static Low Power Verification
- Dynamic Low Power verification
- Advanced UPF-Based Verification
- Hands-On Labs
- Transition from College to Corporate
- Interpersonal Skills and Presentation Skills
- Email Etiquette
- Resume Writing
- Mock Interviews: Technical/HR
- Interview Skills: Group Discussion and HR Round Preparation
- GLS Timing Verification
- GLS TB Setup and Environment
- SDF Annotation
- GLS Overhead
- Improving GLS Performance
- GLS Simulation Debugging
- GLS Regression and Verification Signoff
- Case Study
- Basics of C
- Control Flow and Loops
- Strings
- Pointers
- Arrays
- Functions
- Structures and unions
- Linked Lists
- Accessing Registers
- Hands-On Lab
- PSS Basics
- PSS Constructs
- Test Scenario Modeling
- Coverage in PSS
- Integration with Verification Methodologies
- Advanced PSS Concepts
- Case Study
- Python Programming Basics
- Python Fundamentals for DV
- Python for Regression Testing
- Log Parsing and Report Generation
- Case Study
- Introduction to Gen AI
- Large Language Models
- Prompt Engineering
- Model Fine Tuning and Domain-based models for VLSI
- Gen AI for VLSI
- ML for EDA
- Microchip Polarfire SoC - RISC-V SoC on FPGA